Method of fabricating copper-based semiconductor devices using a sacrificial dielectric layer

ABSTRACT

A method is provided for forming a copper interconnect, the method including forming a sacrificial dielectric layer above a structure layer, forming an opening in the sacrificial dielectric layer and forming a copper layer above the sacrificial dielectric layer and in the opening. The method also includes forming the copper interconnect by removing portions of the copper layer above the sacrificial dielectric layer, leaving the copper interconnect in the opening. The method further includes removing the sacrificial dielectric layer above the structure and adjacent the copper interconnect, and forming a low dielectric constant dielectric layer above the structure and adjacent the copper interconnect.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] This invention relates generally to semiconductor fabricationtechnology, and, more particularly, to techniques for filling contactopenings and vias with copper and creating copper interconnections andlines.

[0003] 2. Description of the Related art

[0004] There is a constant drive within the semiconductor industry toincrease the operating speed of integrated circuit devices, e.g.,microprocessors, memory devices, and the like. This drive is fueled byconsumer demands for computers and electronic devices that operate atincreasingly greater speeds. This demand for increased speed hasresulted in a continual reduction in the size of semiconductor devices,e.g., transistors. That is, many components of a typical field effecttransistor (FET), e.g., channel length, junction depths, gate dielectricthickness, and the like, are reduced. For example, all other thingsbeing equal, the smaller the channel length of the FET, the faster thetransistor will operate. Thus, there is a constant drive to reduce thesize, or scale, of the components of a typical transistor to increasethe overall speed of the transistor, as well as integrated circuitdevices incorporating such transistors. Additionally, reducing the size,or scale, of the components of a typical transistor also increases thedensity, and number, of the transistors that can be produced on a givenamount of wafer real estate, lowering the overall cost per transistor aswell as the cost of integrated circuit devices incorporating suchtransistors.

[0005] However, reducing the size, or scale, of the components of atypical transistor also requires reducing the size and cross-sectionaldimensions of electrical interconnects to contacts to active areas, suchas N⁺ (P⁺) source/drain regions and a doped-polycrystalline silicon(doped-polysilicon or doped-poly) gate conductor, and the like. As thesize and cross-sectional dimensions of electrical interconnects getsmaller, resistance increases and electromigration increases. Increasedresistance and electromigration are undesirable for a number of reasons.For example, increased resistance may reduce device drive current, andsource/drain current through the device, and may also adversely affectthe overall speed and operation of the transistor. Additionally,electromigration effects in aluminum (Al) interconnects, whereelectrical currents actually carry Al atoms along with the current,causing them to electromigrate, may lead to degradation of the Alinterconnects, further increased resistance, and even disconnectionand/or delamination of the Al interconnects.

[0006] The ideal interconnect conductor for semiconductor circuitry willbe inexpensive, easily patterned, have low resistivity, and highresistance to corrosion, electromigration, and stress migration.Aluminum (Al) is most often used for interconnects in contemporarysemiconductor fabrication processes primarily because Al is inexpensiveand easier to etch than, for example, copper (Cu). However, because Alhas poor electromigration characteristics and high susceptibility tostress migration, it is typically necessary to alloy Al with othermetals.

[0007] As discussed above, as semiconductor device geometries shrink andclock speeds increase, it becomes increasingly desirable to reduce theresistance of the circuit metallization. The one criterion that is mostseriously compromised by the use of Al for interconnects is that ofconductivity. This is because the three metals with lower resistivities(Al has a resistivity of 2.824×10⁻⁶ ohms-cm at 20° C.), namely, silver(Ag) with a resistivity of 1.59×10⁻⁶ ohms-cm (at 20° C.), copper (Cu)with a resistivity of 1.73×10⁻⁶ ohms-cm (at 20° C.), and gold (Au) witha resistivity of 2.44×10⁻⁶ ohms-cm (at 20° C.), fall short in othersignificant criteria. Silver, for example, is relatively expensive andcorrodes easily, and gold is very costly and difficult to etch. Copper,with a resistivity nearly on par with silver, immunity fromelectromigration, high ductility (which provides high immunity tomechanical stresses generated by differential expansion rates ofdissimilar materials in a semiconductor chip) and high melting point(1083° C. for Cu vs. 659° C. for Al), fills most criteria admirably.However, Cu is exceedingly difficult to etch in a semiconductorenvironment. As a result of the difficulty in etching Cu, an alternativeapproach to forming vias and metal lines must be used. The damasceneapproach, consisting of etching openings such as trenches in thedielectric for lines and vias and creating in-laid metal patterns, isthe leading contender for fabrication of sub-0.25 micron (sub-0.25μ)design rule Cu-metallized circuits.

[0008] However, the lower resistance and higher conductivity of the Cuinterconnects, coupled with higher device density and, hence, decreaseddistance between the Cu interconnects, may lead to increased capacitancebetween the Cu interconnects. Increased capacitance between the Cuinterconnects, in turn, results in increased RC time delays and longertransient decay times in the semiconductor device circuitry, causingdecreased overall operating speeds of the semiconductor devices.

[0009] One conventional solution to the problem of increased capacitancebetween the Cu interconnects is to use “low dielectric constant” or “lowK” dielectric materials, where K is less than or equal to about 4, forthe interlayer dielectric layers (ILD's) in which the Cu interconnectsare formed using the damascene techniques. However, low K dielectricmaterials are difficult materials to use in conjunction with thedamascene techniques. For example, low K dielectric materials aresusceptible to damage during the etching and subsequent processing stepsused in the damascene techniques.

[0010] The present invention is directed to overcoming, or at leastreducing the effects of, one or more of the problems set forth above.

SUMMARY OF THE INVENTION

[0011] In one aspect of the present invention, a method is provided forforming a copper interconnect, the method including forming asacrificial dielectric layer above a structure layer, forming an openingin the sacrificial dielectric layer and forming a copper layer above thesacrificial dielectric layer and in the opening. The method alsoincludes forming the copper interconnect by removing portions of thecopper layer above the sacrificial dielectric layer, leaving the copperinterconnect in the opening. The method further includes removing thesacrificial dielectric layer above the structure and adjacent the copperinterconnect, and forming a low dielectric constant dielectric layerabove the structure and adjacent the copper interconnect.

BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The invention may be understood by reference to the followingdescription taken in conjunction with the accompanying drawings, inwhich the leftmost significant digit(s) in the reference numeralsdenote(s) the first figure in which the respective reference numeralsappear, and in which:

[0013] FIGS. 1-8 schematically illustrate a single-damascene copperinterconnect process flow according to various embodiments of thepresent invention;

[0014]FIG. 9 schematically illustrates multiple layers of copperinterconnects according to various embodiments of the present invention;

[0015]FIG. 10 schematically illustrates copper interconnects accordingto various embodiments of the present invention connecting source/drainregions of an MOS transistor;

[0016] FIGS. 11-18 schematically illustrate a dual-damascene copperinterconnect process flow according to various embodiments of thepresent invention;

[0017]FIG. 19 schematically illustrates multiple layers of copperinterconnects according to various embodiments of the present invention;and

[0018]FIG. 20 schematically illustrates copper interconnects accordingto various embodiments of the present invention connecting source/drainregions of an MOS transistor.

[0019] While the invention is susceptible to various modifications andalternative forms, specific embodiments thereof have been shown by wayof example in the drawings and are herein described in detail. It shouldbe understood, however, that the description herein of specificembodiments is not intended to limit the invention to the particularforms disclosed, but, on the contrary, the intention is to cover allmodifications, equivalents, and alternatives falling within the spiritand scope of the invention as defined by the appended claims.

DETAILED DESCRIPTION OF SPECIFIC EMBODIMENTS

[0020] Illustrative embodiments of the invention are described below. Inthe interest of clarity, not all features of an actual implementationare described in this specification. It will of course be appreciatedthat in the development of any such actual embodiment, numerousimplementation-specific decisions must be made to achieve thedevelopers' specific goals, such as compliance with system-related andbusiness-related constraints, which will vary from one implementation toanother. Moreover, it will be appreciated that such a development effortmight be complex and time-consuming, but would nevertheless be a routineundertaking for those of ordinary skill in the art having the benefit ofthis disclosure.

[0021] Illustrative embodiments of a method for semiconductor devicefabrication according to the present invention are shown in FIGS. 1-20.Although the various regions and structures of a semiconductor deviceare depicted in the drawings as having very precise, sharpconfigurations and profiles, those skilled in the art recognize that, inreality, these regions and structures are not as precise as indicated inthe drawings. Nevertheless, the attached drawings are included toprovide illustrative examples of the present invention.

[0022] In general, the present invention is directed towards themanufacture of a semiconductor device. As will be readily apparent tothose skilled in the art upon a complete reading of the presentapplication, the present method is applicable to a variety oftechnologies, for example, NMOS, PMOS, CMOS, and the like, and isreadily applicable to a variety of devices, including, but not limitedto, logic devices, memory devices, and the like.

[0023] As shown in FIG. 1, an etch stop layer (ESL) 110 (typicallysilicon nitride, Si₃N₄, or SiN, for short) and an intermetal viaconnection 140 may be formed above a structure 100 such as asemiconducting substrate. However, the present invention is not limitedto the formation of a Cu-based interconnect above the surface of asemiconducting substrate such as a silicon wafer, for example. Rather,as will be apparent to one skilled in the art upon a complete reading ofthe present disclosure, a Cu-based interconnect formed in accordancewith the present invention may be formed above previously formedsemiconductor devices and/or process layer, e.g., transistors, or othersimilar structure. In effect, the present invention may be used to formprocess layers on top of previously formed process layers. The structure100 may be an underlayer of semiconducting material, such as a siliconsubstrate or wafer, or, alternatively, may be an underlayer ofsemiconductor devices (see FIG. 10, for example), such as a layer ofmetal oxide semiconductor field effect transistors (MOSFETs), and thelike, and/or a metal interconnection layer or layers (see FIG. 9, forexample) and/or an interlayer dielectric (ILD) layer or layers, and thelike.

[0024] In a single-damascene copper process flow, according to variousembodiments of the present invention, as shown in FIGS. 1-8, a firstsacrificial dielectric layer 120 is formed above the structure 100,above the ESL 110 and adjacent the intermetal via connection 140. Asecond sacrificial dielectric layer 130 is formed above the firstsacrificial dielectric layer 120 and above the intermetal via connection140. The first sacrificial dielectric layer 120 has the intermetal viaconnection 140 disposed therein. The structure 100 has the ESL 110 (alsoknown as a “hard mask” and typically formed of silicon nitride, Si₃N₄,or SiN, for short) formed and patterned thereon, between the structure100 and the first sacrificial dielectric layer 120 and adjacent theintermetal via connection 140. If necessary, the second sacrificialdielectric layer 130 may be planarized using chemical-mechanicalplanarization (CMP).

[0025] The first and second sacrificial dielectric layers 120 and 130may be formed from a variety of dielectric materials and one or bothmay, for example, be an oxide (e.g., Ge oxide), an oxynitride (e.g., GaPoxynitride), silicon dioxide (SiO₂), a nitrogen-bearing oxide (e.g.,nitrogen-bearing SiO₂), a nitrogen-doped oxide (e.g., N₂-implantedSiO₂), silicon oxynitride (Si_(x)O_(y)N_(z)), and the like. The firstand second sacrificial dielectric layers 120 and 130 may also be formedof any suitable “high dielectric constant” or “high K” material, where Kis greater than or equal to about 8, such as titanium oxide(Ti_(x)O_(y), e.g., TiO₂), tantalum oxide (Ta_(x)O_(y), e.g., Ta₂O₅),barium strontium titanate (BST, BaTiO₃/SrTiO₃), and the like.

[0026] The first and second sacrificial dielectric layers 120 and 130may be formed by a variety of known techniques for forming such layers,e.g., chemical vapor deposition (CVD), low-pressure CVD (LPCVD),plasma-enhanced CVD (PECVD), sputtering, physical vapor deposition(PVD), thermal growing, and the like. The first and second sacrificialdielectric layers 120 and 130 may each have thicknesses in a range ofabout 1000-2500 Å. In one illustrative embodiment, the first and secondsacrificial dielectric layers 120 and 130 are each comprised of silicondioxide (SiO₂) having a thickness of approximately 1000 Å, formed bybeing blanket-deposited by LPCVD process for higher throughput.

[0027] As shown in FIG. 2, a metallization pattern is then formed byusing a patterned photomask 150 (FIGS. 1-2) and photolithography. Forexample, openings (such as trench 220) for conductive metal lines,contact holes, via holes, and the like, are etched into the secondsacrificial dielectric layer 130 (FIG. 2). The opening 220 may be formedby using a variety of known anisotropic etching techniques, such as areactive ion etching (RIE) process using hydrogen bromide (HBr) andargon (Ar) as the etchant gases, for example. Alternatively, an RIEprocess with CHF₃ and Ar as the etchant gases may be used, for example.Dry etching may also be used, in various illustrative embodiments.

[0028] As shown in FIG. 3, the patterned photomask 150 is then strippedand a thin barrier metal layer of tantalum (Ta) 325A and a copper seedlayer 325B are then applied to the entire surface using vapor-phasedeposition (FIG. 3). The barrier metal layer of Ta 325A and the Cu seedlayer 325B blanket-deposit an entire upper surface 330 of the secondsacrificial dielectric layer 130 as well as side 340 and bottom 350surfaces of the trench 220, forming a conductive surface 335, as shownin FIG. 3.

[0029] The barrier metal layer 325A may be formed of at least one layerof a barrier metal material, such as tantalum or tantalum nitride, andthe like. For example, the barrier metal layer 325A may equivalently beformed of titanium nitride, titanium-tungsten, nitridedtitanium-tungsten, magnesium, or another suitable barrier material. Thecopper seed layer 325B may be formed on top of the one or more barriermetal layers 325A by physical vapor deposition (PVD) or chemical vapordeposition (CVD), for example.

[0030] The bulk of the copper trench-fill is frequently done using anelectroplating technique, where the conductive surface 335 ismechanically clamped to an electrode to establish an electrical contact,and the structure 100 is then immersed in an electrolyte solutioncontaining Cu ions. An electrical current is then passed through thewafer-electrolyte system to cause reduction and deposition of Cu on theconductive surface 335. In addition, an alternating-current bias of thewafer-electrolyte system has been considered as a method ofself-planarizing the deposited Cu film, similar to the deposit-etchcycling used in high-density plasma (HDP) tetraethyl orthosilicate(TEOS) dielectric depositions.

[0031] As shown in FIG. 4, this process typically produces a conformalcoating of Cu 440 of substantially constant thickness across the entireconductive surface 335. As shown in FIG. 5, once a sufficiently thicklayer of Cu 440 has been deposited, the layer of Cu 440 is planarizedusing CMP techniques. The planarization using CMP clears all Cu and Tabarrier metal from the entire upper surface 330 of the secondsacrificial dielectric layer 130, leaving Cu 440 only in Cu-filledtrench 545, adjacent remaining portions 525A and 525B of the one or morebarrier metal layers 325A and copper seed layer 325B (FIGS. 3 and 4),respectively, as shown in FIG. 5.

[0032] As shown in FIG. 6, the first and second sacrificial dielectriclayers 120 and 130 may be removed by using a wet etch, for example,leaving a Cu-interconnect 645 remaining. The wet etch stops at the etchstop layer (ESL) 110. Dry etching and/or plasma etching may also beused, in various alternative illustrative embodiments. The first andsecond sacrificial dielectric layers 120 and 130 may also be selectivelyremoved, for example, by stripping with hot phosphoric acid (H₃PO₄). TheCu-interconnect 645 may include the Cu 440 in the Cu-filled trench 545,adjacent the remaining portions 525A and 525B of the one or more barriermetal layers 325A and copper seed layer 325B (FIGS. 3 and 4), and theintermetal via connection 140.

[0033] As shown in FIG. 7, a “low dielectric constant” or “low K” (K isless than or equal to about 4) dielectric layer 700 may be formedadjacent the Cu-interconnect 645 and above the ESL 110. The low Kdielectric layer 700 may be formed by a variety of known techniques forforming such layers, e.g., chemical vapor deposition (CVD), low-pressureCVD (LPCVD), plasma-enhanced CVD (PECVD), sputtering, physical vapordeposition (PVD), thermal growing, and the like, and may have athickness ranging from approximately 2000 Å-5000 Å, for example.

[0034] The low K dielectric layer 700 may be formed from a variety oflow K dielectric materials, where K is less than or equal to about 4.Examples include Applied Material's Black Diamond®, Novellus' Coral®,Allied Signal's Nanoglass®, JSR's LKD5104, and the like. In oneillustrative embodiment, the low K dielectric layer 700 is comprised ofmethylene silicon hydroxide, having a thickness of approximately 2500 Å,which is formed by being blanket-deposited by an LPCVD process forhigher throughput.

[0035] As shown in FIG. 8, the low K dielectric layer 700 is planarizedusing CMP techniques, forming a planarized low K dielectric layer 810.The planarization leaves the planarized low K dielectric layer 810adjacent the Cu-interconnect 645 and above the ESL 110, forming aCu-interconnect layer 800. The Cu-interconnect layer 800 may include theCu-interconnect 645 adjacent the planarized low K dielectric layer 810.The Cu-interconnect layer 800 may also include the ESL 110. As shown inFIG. 8, the Cu-interconnect layer 800 may also include an ESL 820 (alsoknown as a “hard mask” and typically formed of silicon nitride, Si₃N₄,or SiN, for short) formed and patterned above the planarized low Kdielectric layer 810 and above at least a portion of the Cu-interconnect645.

[0036] As shown in FIG. 9, the Cu-interconnect layer 800 may be anunderlying structure layer (similar to the structure 100) to aCu-interconnect layer 900. The Cu-interconnect layer 900 may include aCu-filled trench 940 and an intermetal via connection 910 adjacent aplanarized low K dielectric layer 905. The Cu-interconnect layer 900 mayalso include the ESL 820 and/or an ESL 920 (also known as a “hard mask”and typically formed of silicon nitride, Si₃N₄, or SiN, for short)formed and patterned above the planarized low K dielectric layer 905 andabove at least a portion of the Cu-filled trench 940.

[0037] As shown in FIG. 10, an MOS transistor 1010 may be an underlyingstructure layer (similar to the structure 100) to a Cu-interconnectlayer 1000. The Cu-interconnect layer 1000 may include Cu-filledtrenches 1020 and intermetal via connections 1030 adjacent a planarizedlow K dielectric layer 1040.

[0038] As shown in FIG. 11, a first etch stop layer (ESL) 1110(typically silicon nitride, Si₃N₄, or SiN, for short) and a firstsacrificial dielectric layer 1120 may be formed above a structure 1100such as a semiconducting substrate. However, the present invention isnot limited to the formation of a Cu-based interconnect above thesurface of a semiconducting substrate such as a silicon wafer, forexample. Rather, as will be apparent to one skilled in the art upon acomplete reading of the present disclosure, a Cu-based interconnectformed in accordance with the present invention may be formed abovepreviously formed semiconductor devices and/or process layer, e.g.,transistors, or other similar structure. In effect, the presentinvention may be used to form process layers on top of previously formedprocess layers. The structure 1100 may be an underlayer ofsemiconducting material, such as a silicon substrate or wafer, or,alternatively, may be an underlayer of semiconductor devices (see FIG.20, for example), such as a layer of metal oxide semiconductor fieldeffect transistors (MOSFETs), and the like, and/or a metalinterconnection layer or layers (see FIG. 19, for example) and/or aninterlayer dielectric (ILD) layer or layers, and the like.

[0039] In a dual-damascene copper process flow, according to variousembodiments of the present invention, as shown in FIGS. 11-18, a firstsacrificial dielectric layer 1120 is formed above the structure 1100,above the first ESL 1110. A second sacrificial dielectric layer 1130 isformed above the first sacrificial dielectric layer 1120 and above asecond ESL 1115. As will be described in more detail below inconjunction with FIG. 12, the first ESL 1110 and the second ESL 1115define a lower (via) portion of the copper interconnect formed in thedual-damascene copper process flow. The structure 1100 has the first ESL1110 (also known as a “hard mask” and typically formed of siliconnitride, Si₃N₄, or SiN, for short) formed and patterned thereon, betweenthe structure 1100 and the first sacrificial dielectric layer 1120.Similarly, the first sacrificial dielectric layer 1120 has the secondESL 1115 (also typically formed of SiN) formed and patterned thereon,between the first sacrificial dielectric layer 1120 and the secondsacrificial dielectric layer 1130. If necessary, the second sacrificialdielectric layer 1130 may be planarized using chemical-mechanicalplanarization (CMP).

[0040] The first and second sacrificial dielectric layers 1120 and 1130may be formed from a variety of dielectric materials and one or bothmay, for example, be an oxide (e.g., Ge oxide), an oxynitride (e.g., GaPoxynitride), silicon dioxide (SiO₂), a nitrogen-bearing oxide (e.g.,nitrogen-bearing SiO₂), a nitrogen-doped oxide (e.g., N₂-implantedSiO₂), silicon oxynitride (Si_(x)O_(y)N_(z)), and the like. The firstand second sacrificial dielectric layers 1120 and 1130 may also beformed of any suitable “high dielectric constant” or “high K” material,where K is greater than or equal to about 8, such as titanium oxide(Ti_(x)O_(y), e.g., TiO₂), tantalum oxide (Ta_(x)O_(y), e.g., Ta₂O₅),barium strontium titanate (BST, BaTiO₃/SrTiO₃), and the like.

[0041] The first and second sacrificial dielectric layers 1120 and 1130may be formed by a variety of known techniques for forming such layers,e.g., chemical vapor deposition (CVD), low-pressure CVD (LPCVD),plasma-enhanced CVD (PECVD), sputtering, physical vapor deposition(PVD), thermal growing, and the like. The first and second sacrificialdielectric layers 1120 and 1130 may each have thicknesses in a range ofabout 1000-2500 Å. In one illustrative embodiment, the first and secondsacrificial dielectric layers 1120 and 1130 are each comprised ofsilicon dioxide (SiO₂) having a thickness of approximately 1000 Å,formed by being blanket-deposited by LPCVD process for higherthroughput.

[0042] As shown in FIG. 12, a metallization pattern is then formed byusing a patterned photomask 1150 (FIGS. 11-12) and photolithography. Forexample, first and second openings, such as via 1220 and trench 1230,for conductive metal lines, contact holes, via holes, and the like, areetched into first and second sacrificial dielectric layers 1120 and1130, respectively (FIG. 12). The first and second openings 1220 and1230 may be formed by using a variety of known anisotropic etchingtechniques, such as a reactive ion etching (RIE) process using hydrogenbromide (HBr) and argon (Ar) as the etchant gases, for example.Alternatively, an RIE process with CHF₃ and Ar as the etchant gases maybe used, for example. Dry etching may also be used, in variousillustrative embodiments.

[0043] As shown in FIG. 13, the patterned photomask 1150 is thenstripped and a thin barrier metal layer of tantalum (Ta) 1325A and acopper seed layer 1325B are then applied to the entire surface usingvapor-phase deposition (FIG. 13). The barrier metal layer of Ta 1325Aand the Cu seed layer 1325B blanket-deposit the entire upper surface1330 of the second sacrificial dielectric layer 1130 as well as the side1340 and bottom 1350 surfaces of the first and second openings 1220 and1230, forming a conductive surface 1335, as shown in FIG. 13.

[0044] The barrier metal layer 1325A may be formed of at least one layerof a barrier metal material, such as tantalum or tantalum nitride, andthe like. For example, the barrier metal layer 1325A may equivalently beformed of titanium nitride, titanium-tungsten, nitridedtitanium-tungsten, magnesium, or another suitable barrier material. Thecopper seed layer 1325B may be formed on top of the one or more barriermetal layers 1325A by physical vapor deposition (PVD) or chemical vapordeposition (CVD), for example.

[0045] The bulk of the copper trench-fill is frequently done using anelectroplating technique, where the conductive surface 1335 ismechanically clamped to an electrode to establish an electrical contact,and the structure 1100 is then immersed in an electrolyte solutioncontaining Cu ions. An electrical current is then passed through thewafer-electrolyte system to cause reduction and deposition of Cu on theconductive surface 1335. In addition, an alternating-current bias of thewafer-electrolyte system has been considered as a method ofself-planarizing the deposited Cu film, similar to the deposit-etchcycling used in high-density plasma (HDP) tetraethyl orthosilicate(TEOS) dielectric depositions.

[0046] As shown in FIG. 14, this process typically produces a conformalcoating of Cu 1440 of substantially constant thickness across the entireconductive surface 1335. As shown in FIG. 15, once a sufficiently thicklayer of Cu 1440 has been deposited, the layer of Cu 1440 is planarizedusing CMP techniques. The planarization using CMP clears all Cu and Tabarrier metal from the entire upper surface 1330 of the secondsacrificial dielectric layer 1130, leaving Cu 1440 only in Cu-filledtrench and via 1545, adjacent remaining portions 1525A and 1525B of theone or more barrier metal layers 1325A and copper seed layer 1325B(FIGS. 13 and 14), respectively, as shown in FIG. 15.

[0047] As shown in FIG. 16, the first and second sacrificial dielectriclayers 1120 and 1130 may be removed by using a wet etch, for example,leaving the Cu-interconnect 1645 remaining. The wet etch stops at thefirst etch stop layer (ESL) 1110. Dry etching and/or plasma etching mayalso be used, in various alternative illustrative embodiments. The firstand second sacrificial dielectric layers 1120 and 1130 may also beselectively removed, for example, by stripping with hot phosphoric acid(H₃PO₄). The Cu-interconnect 1645 may include the Cu 1440 in theCu-filled trench and via 1545, adjacent the remaining portions 1525A and1525B of the one or more barrier metal layers 1325A and copper seedlayer 1325B (FIGS. 13 and 14).

[0048] As shown in FIG. 17, a “low dielectric constant” or “low K” (K isless than or equal to about 4) dielectric layer 1700 may be formedadjacent the Cu-interconnect 1645 and above the first ESL 1110. The lowK dielectric layer 1700 may be formed by a variety of known techniquesfor forming such layers, e.g., chemical vapor deposition (CVD),low-pressure CVD (LPCVD), plasma-enhanced CVD (PECVD), sputtering,physical vapor deposition (PVD), thermal growing, and the like, and mayhave a thickness ranging from approximately 2000 Å-5000 Å, for example.

[0049] The low K dielectric layer 1700 may be formed from a variety oflow K dielectric materials, where K is less than or equal to about 4.Examples include Applied Material's Black Diamond®, Novellus' Coral®,Allied Signal's Nanoglass®, JSR's LKD5104, and the like. In oneillustrative embodiment, the low K dielectric layer 1700 is comprised ofmethylene silicon hydroxide, having a thickness of approximately 2500 Å,which is formed by being blanket-deposited by an LPCVD process forhigher throughput.

[0050] As shown in FIG. 18, the low K dielectric layer 1700 isplanarized using CMP techniques, forming a planarized low K dielectriclayer 1810. The planarization leaves the planarized low K dielectriclayer 1810 adjacent the Cu-interconnect 1645 and above the first ESL1110, forming a Cu-interconnect layer 1800. The Cu-interconnect layer1800 may include the Cu-interconnect 1645 adjacent the planarized low Kdielectric layer 1810. The Cu-interconnect layer 1800 may also includethe first ESL 1110. As shown in FIG. 18, the Cu-interconnect layer 1800may also include a third ESL 1820 (also known as a “hard mask” andtypically formed of silicon nitride, Si₃N₄, or SiN, for short) formedand patterned above the planarized low K dielectric layer 1810 and aboveat least a portion of the Cu-interconnect 1645.

[0051] As shown in FIG. 19, the Cu-interconnect layer 1800 may be anunderlying structure layer (similar to the structure 1100) to aCu-interconnect layer 1900. The Cu-interconnect layer 1900 may include aCu-filled trench 1940 and an intermetal via connection 1910 adjacent aplanarized low K dielectric layer 1905. The Cu-interconnect layer 1900may also include the third ESL 1820 and/or a fourth ESL 1920 (also knownas a “hard mask” and typically formed of silicon nitride, Si₃N₄, or SiN,for short) formed and patterned above the planarized low K dielectriclayer 1905 and above at least a portion of the Cu-filled trench 1940.Alternatively, the Cu-interconnect layer 1900 may be similar to theCu-interconnect layer 1800, having a Cu-interconnect disposed thereinthat is similar to the Cu-interconnect 1645, for example.

[0052] As shown in FIG. 20, an MOS transistor 2010 may be an underlyingstructure layer (similar to the structure 1100) to a Cu-interconnectlayer 1000. The Cu-interconnect layer 1000 may include Cu-filledtrenches and vias 2020 adjacent a planarized low K dielectric layer2040.

[0053] The dual-damascene copper process flow according to variousembodiments of the present invention, as shown in FIGS. 11-18, combinesthe intermetal via connection formation with the Cu trench-fillformation by etching a more complex pattern before the formation of thebarrier metal layer and Cu seed layer and before the Cu trench-fill. Thetrench etching continues until the via hole (such as the first opening1220 in FIG. 12) has been etched out. The rest of the dual-damascenecopper process flow according to various embodiments of the presentinvention, as shown in FIGS. 13-18, is essentially identical with thecorresponding single-damascene copper process flow according to variousembodiments of the present invention, as shown in FIGS. 3-8. Overall,however, the dual-damascene copper process flow according to variousembodiments of the present invention significantly reduces the number ofprocessing steps and is a preferred method of achievingCu-metallization.

[0054] Any of the above-disclosed embodiments of a method of forming acopper interconnect enables a copper interconnect to be formed usingconventional damascene techniques in conjunction with sacrificialdielectric materials that are far more robust than the conventional lowK materials typically used in conventional damascene techniques. Thesacrificial dielectric materials are far less susceptible to damageduring the etching and subsequent processing steps of the conventionaldamascene techniques than are the conventional low K materials. Byremoving the sacrificial dielectric materials after the copperinterconnect has been formed and then forming a low K dielectric layeradjacent the copper interconnect, all of the advantages of using a low Kdielectric layer to reduce the capacitance and RC delays betweenadjacent copper interconnects are retained, without any of thedifficulties of forming the copper interconnect using a low K dielectricduring the conventional damascene processing.

[0055] The particular embodiments disclosed above are illustrative only,as the invention may be modified and practiced in different butequivalent manners apparent to those skilled in the art having thebenefit of the teachings herein. Furthermore, no limitations areintended to the details of construction or design herein shown, otherthan as described in the claims below. It is therefore evident that theparticular embodiments disclosed above may be altered or modified andall such variations are considered within the scope and spirit of theinvention. Accordingly, the protection sought herein is as set forth inthe claims below.

What is claimed:
 1. A method of forming a copper interconnect, themethod comprising: forming a sacrificial dielectric layer above astructure layer; forming an opening in the sacrificial dielectric layer;forming a copper layer above the sacrificial dielectric layer and in theopening; forming the copper interconnect by removing portions of thecopper layer above the sacrificial dielectric layer, leaving the copperinterconnect in the opening; removing the sacrificial dielectric layerabove the structure and adjacent the copper interconnect; and forming alow dielectric constant dielectric layer above the structure andadjacent the copper interconnect.
 2. The method of claim 1, furthercomprising: planarizing the low dielectric constant dielectric layer. 3.The method of claim 1, wherein forming the low dielectric constantdielectric layer includes forming the low dielectric constant dielectriclayer out of a low dielectric constant (low K) dielectric material,having a dielectric constant K of at most about four.
 4. The method ofclaim 1, further comprising: forming and patterning a mask layer abovethe low dielectric constant dielectric layer to have a mask layeropening above at least a portion of the copper interconnect.
 5. Themethod of claim 1, wherein forming the low dielectric constantdielectric layer includes forming the low dielectric constant dielectriclayer using one of chemical vapor deposition (CVD), low-pressure CVD(LPCVD), plasma-enhanced CVD (PECVD), sputtering, physical vapordeposition (PVD), and thermal growing.
 6. The method of claim 1, whereinforming the sacrificial dielectric layer includes forming thesacrificial dielectric layer out of one of an oxide, an oxynitride,silicon dioxide, a nitrogen-bearing oxide, a nitrogen-doped oxide,silicon oxynitride, a high dielectric constant (high K), where K is atleast about 8, titanium oxide, tantalum oxide, barium strontiumtitanate, and forming the sacrificial dielectric layer using one ofchemical vapor deposition (CVD), low-pressure CVD (LPCVD),plasma-enhanced CVD (PECVD), sputtering, physical vapor deposition(PVD), and thermal growing.
 7. The method of claim 1, wherein formingthe opening in the sacrificial dielectric layer includes forming theopening in the sacrificial dielectric layer using one of a mask ofphotoresist and an etch stop layer, the one of the mask of photoresistand the etch stop layer being formed and patterned above the sacrificialdielectric layer.
 8. The method of claim 7, wherein using the one of themask of photoresist and the etch stop layer includes using an etch stoplayer formed of silicon nitride.
 9. The method of claim 1, whereinforming the copper layer includes forming the copper layer usingelectrochemical deposition of copper.
 10. The method of claim 9, whereinusing the electrochemical deposition of the copper includes forming atleast one barrier layer and a copper seed layer in the second openingbefore the electrochemical deposition of the copper, and planarizing thecopper using chemical mechanical polishing after the electrochemicaldeposition of the copper.
 11. A method of forming a copper interconnect,the method comprising: forming a sacrificial dielectric layer above astructure layer; forming an opening in the sacrificial dielectric layer;forming at least one barrier metal layer and a copper seed layer abovethe sacrificial dielectric layer and in the opening; electrochemicallydepositing copper above the copper seed layer above the at least onebarrier metal layer; forming the copper interconnect by removing thecopper and the at least one barrier metal layer and the copper seedlayer above the sacrificial dielectric layer, leaving the copperinterconnect in the opening; removing the sacrificial dielectric layerabove the structure and adjacent the copper interconnect; and forming alow dielectric constant dielectric layer above the structure andadjacent the copper interconnect.
 12. The method of claim 11, furthercomprising: planarizing the low dielectric constant dielectric layer.13. The method of claim 11, wherein forming the low dielectric constantdielectric layer includes forming the low dielectric constant dielectriclayer out of a low dielectric constant (low K) dielectric material,having a dielectric constant K of at most about four.
 14. The method ofclaim 11, further comprising: forming and patterning a mask layer abovethe low dielectric constant dielectric layer to have a mask layeropening above at least a portion of the copper interconnect.
 15. Themethod of claim 11, wherein forming the low dielectric constantdielectric layer includes forming the low dielectric constant dielectriclayer using one of chemical vapor deposition (CVD), low-pressure CVD(LPCVD), plasma-enhanced CVD (PECVD), sputtering, physical vapordeposition (PVD), and thermal growing.
 16. The method of claim 11,wherein forming the sacrificial dielectric layer includes forming thesacrificial dielectric layer out of one of an oxide, an oxynitride,silicon dioxide, a nitrogen-bearing oxide, a nitrogen-doped oxide,silicon oxynitride, a high dielectric constant (high K), where K is atleast about 8, titanium oxide, tantalum oxide, barium strontiumtitanate, and forming the sacrificial dielectric layer using one ofchemical vapor deposition (CVD), low-pressure CVD (LPCVD),plasma-enhanced CVD (PECVD), sputtering, physical vapor deposition(PVD), and thermal growing.
 17. The method of claim 11, wherein formingthe opening in the sacrificial dielectric layer includes forming theopening in the sacrificial dielectric layer using one of a mask ofphotoresist and an etch stop layer, the one of the mask of photoresistand the etch stop layer being formed and patterned above the sacrificialdielectric layer.
 18. The method of claim 17, wherein using the one ofthe mask of photoresist and the etch stop layer includes using an etchstop layer formed of silicon nitride.
 19. The method of claim 11,wherein removing the copper and the at least one barrier metal layer andthe copper seed layer includes planarizing the copper.
 20. The method ofclaim 19, wherein planarizing the copper includes using chemicalmechanical polishing.
 21. A method of forming a copper interconnect, themethod comprising: forming a first sacrificial dielectric layer above astructure layer; forming a second sacrificial dielectric layer above thefirst sacrificial dielectric layer; forming a first opening in the firstsacrificial dielectric layer and a second opening in the secondsacrificial dielectric layer; forming a copper layer above the first andsecond sacrificial dielectric layers and in the first and secondopenings; forming the copper interconnect by removing portions of thecopper layer above the second sacrificial dielectric layer, leaving thecopper interconnect in the first and second openings; removing the firstand second sacrificial dielectric layers above the structure andadjacent the copper interconnect; and forming a low dielectric constantdielectric layer above the structure and adjacent the copperinterconnect.
 22. The method of claim 21, further comprising:planarizing the low dielectric constant dielectric layer.
 23. The methodof claim 21, wherein forming the low dielectric constant dielectriclayer includes forming the low dielectric constant dielectric layer outof a low dielectric constant (low K) dielectric material, having adielectric constant K of at most about four.
 24. The method of claim 21,further comprising: forming and patterning a mask layer above the lowdielectric constant dielectric layer to have a mask layer opening aboveat least a portion of the copper interconnect.
 25. The method of claim21, wherein forming the low dielectric constant dielectric layerincludes forming the low dielectric constant dielectric layer using oneof chemical vapor deposition (CVD), low-pressure CVD (LPCVD),plasma-enhanced CVD (PECVD), sputtering, physical vapor deposition(PVD), and thermal growing.
 26. The method of claim 21, wherein formingthe first and second sacrificial dielectric layers includes forming thefirst and second sacrificial dielectric layers out of at least one of anoxide, an oxynitride, silicon dioxide, a nitrogen-bearing oxide, anitrogen-doped oxide, silicon oxynitride, a high dielectric constant(high K), where K is at least about 8, titanium oxide, tantalum oxide,barium strontium titanate, and forming the first and second sacrificialdielectric layers using at least one of chemical vapor deposition (CVD),low-pressure CVD (LPCVD), plasma-enhanced CVD (PECVD), sputtering,physical vapor deposition (PVD), and thermal growing.
 27. The method ofclaim 21, wherein forming the first and second openings in the first andsecond sacrificial dielectric layers includes forming the first andsecond openings in the first and second sacrificial dielectric layersusing an etch stop layer and a mask of photoresist, respectively, theetch stop layer and the mask of photoresist being formed and patternedabove the first and second sacrificial dielectric layers, respectively.28. The method of claim 27, wherein using the at least one of the maskof photoresist and the etch stop layer includes using at least one etchstop layer formed of silicon nitride.
 29. The method of claim 21,wherein forming the copper layer includes forming the copper layer usingelectrochemical deposition of copper.
 30. The method of claim 29,wherein using the electrochemical deposition of the copper includesforming at least one barrier layer and a copper seed layer in the secondopening before the electrochemical deposition of the copper, andremoving the portions of the copper layer includes planarizing thecopper using chemical mechanical polishing after the electrochemicaldeposition of the copper.
 31. A method of forming a copper interconnect,the method comprising: forming a first sacrificial dielectric layerabove a structure layer; forming a second sacrificial dielectric layerabove the first sacrificial dielectric layer; forming a first opening inthe first sacrificial dielectric layer and a second opening in thesecond sacrificial dielectric layer; forming at least one barrier metallayer and a copper seed layer above the first and second sacrificialdielectric layers and in the first and second openings;electrochemically depositing copper above the copper seed layer abovethe at least one barrier metal layer; forming the copper interconnect byremoving the copper and the at least one barrier metal layer and thecopper seed layer above the second sacrificial dielectric layer, leavingthe copper interconnect in the first and second openings; removing thefirst and second sacrificial dielectric layers above the structure andadjacent the copper interconnect; and forming a low dielectric constantdielectric layer above the structure and adjacent the copperinterconnect.
 32. The method of claim 31, further comprising:planarizing the low dielectric constant dielectric layer.
 33. The methodof claim 31, wherein forming the low dielectric constant dielectriclayer includes forming the low dielectric constant dielectric layer outof a low dielectric constant (low K) dielectric material, having adielectric constant K of at most about four.
 34. The method of claim 31,further comprising: forming and patterning a mask layer above the lowdielectric constant dielectric layer to have a mask layer opening aboveat least a portion of the copper interconnect.
 35. The method of claim31, wherein forming the low dielectric constant dielectric layerincludes forming the low dielectric constant dielectric layer using oneof chemical vapor deposition (CVD), low-pressure CVD (LPCVD),plasma-enhanced CVD (PECVD), sputtering, physical vapor deposition(PVD), and thermal growing.
 36. The method of claim 31, wherein formingthe first and second sacrificial dielectric layers includes forming thefirst and second sacrificial dielectric layers out of at least one of anoxide, an oxynitride, silicon dioxide, a nitrogen-bearing oxide, anitrogen-doped oxide, silicon oxynitride, a high dielectric constant(high K), where K is at least about 8, titanium oxide, tantalum oxide,barium strontium titanate, and forming the first and second sacrificialdielectric layers using at least one of chemical vapor deposition (CVD),low-pressure CVD (LPCVD), plasma-enhanced CVD (PECVD), sputtering,physical vapor deposition (PVD), and thermal growing.
 37. The method ofclaim 31, wherein forming the first and second openings in the first andsecond sacrificial dielectric layers includes forming the first andsecond openings in the first and second sacrificial dielectric layersusing an etch stop layer and a mask of photoresist, respectively, theetch stop layer and the mask of photoresist being formed and patternedabove the first and second sacrificial dielectric layers, respectively.38. The method of claim 37, wherein using the at least one of the maskof photoresist and the etch stop layer includes using at least one etchstop layer formed of silicon nitride.
 39. The method of claim 31,wherein removing the copper and the at least one barrier metal layer andthe copper seed layer includes planarizing the copper.
 40. The method ofclaim 39, wherein planarizing the copper includes using chemicalmechanical polishing.